module led
	(
		input wire CLK_IN,	
        input wire RST_N,
		output wire LED0,        
		output wire LED1,        
		output wire LED2

	);

	reg [26:0] count;
    wire sysclk;	
    wire [31:0] instruction;
	
	initial
	begin
		count=27'b0;
	end		
		
	PLL clkpll(		
		.refclk (CLK_IN),	
		.reset (~RST_N),	
		.clk0_out (sysclk)		
	);

//	always @(posedge CLK_IN)begin
	always @(posedge sysclk)begin
		count <= count + 1'b1;
	end
		
	I_ROM instruction_rom (		
		.addra (count[26:23]),		
		.rsta (1'b0),		
		.clka (sysclk),
		.doa (instruction)		
	);	
	
//	assign LED1 = count[25];
	assign LED0 = instruction[0];
	assign LED1 = ~instruction[1];
	assign LED2 = ~instruction[2];
//	assign LED1 = 1'b1;
//	assign LED2 = 1'b1;

endmodule
